The present invention relates generally to switch-mode power converters. More particularly, the present invention relates to methods and devices for providing an isolated drive circuit integrated into a power transformer or power inductor.
A switch-mode power converter typically uses an inductor, a transformer, a capacitor, or some combination thereof, as energy storage elements to transfer energy from an input source to an output load in discrete pulses. Additional circuitry is added to maintain a constant voltage or constant current within load limits of the circuit. Using a transformer allows the output to be electrically isolated from the input source.
New challenges in the industry for DC/DC power supply designers demand higher efficiency and power density. This has resulted in the use of synchronous rectifiers that are implemented by replacing rectifying diodes in the output with MOSFET devices.
Using self-driven synchronous rectifiers in various converter topologies is attractive and popular because of their simplicity. This is primarily due to a lack of need for additional isolation between drive signals for the input side switches and the synchronous rectifiers. However, simplicity has its drawbacks. These drawbacks include: (a) cross conduction between the synchronous rectifiers and the primary side switches; (b) the drive voltage, being derived from a power transformer, varies with changes in input voltage and thus requires additional clamp circuitry and results in additional losses; and (c) the timing between the drive signals depends heavily on circuit parasitics.
One solution is to use direct drive for the synchronous rectifiers with well-controlled timing between the drive signals for the main switches (input side) and the synchronous rectifiers (output side). This solution thus allows for efficient operation of the synchronous rectifiers even at high switching frequencies. Yet another benefit of direct driven synchronous rectifiers is that the drive voltage (gate to source) is constant and independent of input voltage, further improving efficiency over a wide input voltage range.
Various isolated drive circuits have been proposed in the prior art. The most common technique for providing isolation is the use of a drive transformer. Various solutions using a drive transformer have been proposed, all of which require a separate magnetic core for the drive transformer.
One solution is proposed in U.S. Pat. No. 5,907,481 by Svardsjo in which a PWM signal is fed into a switch control circuit for the primary side switches and into a drive transformer with it outputs feeding a switch control circuit for the synchronous rectifiers. A disadvantage of this solution is that the drive transformer only transfers the PWM signal from one side of the converter to the other side and requires additional switch control circuitry as well as a power source for the driving switches.
In U.S. Pat. Nos. 6,804,125 and 7,102,898, Brkovic proposed an improved isolated drive circuit using a drive transformer which provides power and appropriate delays to the primary switches and the synchronous rectifiers. This circuit takes advantage of the leakage inductance of the drive transformer windings as well as the input capacitance of the primary switches (MOSFETs) to provide the necessary delays. The circuitry further discloses means to disable or enable the primary winding from a condition sensed on the secondary side even with a control and feedback circuit located on the output side.
A prior art isolated DC-to-DC converter which employs a double ended DC-to-DC converter having a half-bridge primary circuit and a full-wave secondary circuit employing synchronous rectifiers S1 and S2 is shown in FIG. 1. The circuit in FIG. 1 includes switches Q1 and Q2 (also called primary controllable power switches), capacitors C1 and C2, a power isolation transformer T1, synchronous rectifiers S1 and S2, output inductor Lo, and capacitor Co. The input voltage VIN is split with filtering capacitors C1 and C2. One end of primary winding Np of transformer T1 is connected to the common node of capacitors C1 and C2 while the second end is connected to the common node of switches Q1 and Q2. Two secondary windings NS1 and NS2 are center tapped at a common node CT. The common node CT is connected to a low pass output filter including inductor Lo and capacitor Co connected across the output of the converter and a load. The second end of winding NS1 is connected to synchronous rectifier S1 while the second end of winding NS2 is connected to synchronous rectifier S2. The polarity of the windings of transformer T1 is chosen such that when switch Q1 is on, synchronous rectifier S1 is on and S2 is off. Conversely, when switch Q2 is on, synchronous rectifier S1 is off and S2 is on. Primary switches Q1 and Q2 are exemplified as MOSFETs (commonly used today) but may be also realized as IGBTs or other controllable switches.
The output voltage VOUT is fed into a CONTROL CIRCUIT which generates two output signals OUTA and OUTB having a 180° phase shift that are fed into a SWITCH CONTROL CIRCUIT which generates four signals GQ1, GQ2, GS1 and GS2 for driving switches Q1, Q2, S1 and S2, respectively.
The salient waveforms demonstrating operation of the circuitry in the converter shown in FIG. 1 are illustrated in FIG. 2. It is assumed, for simplicity of explanation, that all voltage waveforms (except OUTA and OUTB) have finite rise and fall times and that all switches have threshold voltages at one-half of the voltage amplitude of the drive signals. Also, the rise and fall times are exaggerated relative to switching period TS for purpose of explanation.
In the waveforms of FIG. 2:                td1 represents the time interval between turning-off synchronous rectifier S2 and turning-on switch Q1.        td2 represents the time interval between turning-off switch Q1 and turning-on synchronous rectifier S2.        td3 represents the time interval between turning-off synchronous rectifier S1 and turning-on switch Q2. In practice, usually td1≈td3.        td4 represents the time interval between turning-off switch Q2 and turning-on synchronous rectifier S1. In practice, usually td2≈td4.        ta represents the rise time of VG1 from zero to threshold voltage of switch Q1. This is also the time during which voltage VG1 is non-zero and positive, while voltage VP is still zero.        tb represents the fall time of VG1 from drive voltage to the threshold voltage of switch Q1. This is also the time during which voltage VG1 is non-zero and positive while voltage VP is non-zero and still positive (VIN/2).        tc represents the rise time of VG2 from drive voltage to the threshold voltage of switch Q2. This is also the time during which voltage VG2 is non-zero and positive, while voltage VP is still zero.        td represents the fall time of VG2 from drive voltage to the threshold voltage of switch Q2. This is also the time during which voltage VG2 is non-zero and positive while voltage VP is non-zero and negative (−VIN/2).        tp represents the time during which Q1 is on, voltage VP is positive (VIN/2), voltage VS2 is positive, and S2 is off.        tn represents the time during which Q2 is on, voltage VP is negative (−VIN/2), voltage VS1 is positive, and S1 is off.        
TS represents the switching period of the converter.
D represents the duty cycle of the logic signals OUTA and OUTB and is defined as a portion of the half of the switching period TS during which signal OUTA or OUTB are logic high. OUTA and OUTB are phase shifted by 180°, and are never at a logic high at the same time.
At t=0, signal OUTA becomes high, while signal OUTB is low. At the same moment, voltage VGS2 begins falling and when it drops to zero, voltage VG1 begins rising. After time ta, voltage VG1 reaches the threshold voltage of Q1, and Q1 is turned-on. At that moment, voltage VP starts rising to its positive value VIN/2. Note that during time ta, voltage VP is still zero (shorted by the output inductor current flowing in both secondary windings NS1 and NS2 in opposite directions). During time tp, power is transferred from the input VIN to the output VOUT of the converter through switch Q1, primary winding Np, secondary winding NS1, synchronous rectifier S1 and output inductor Lo.
At t=DTS/2, signal OUTA becomes zero (logic low), signal OUTB is still low, voltage VG1 starts falling and after time tb, reaches the turn-off threshold of switch Q1, and Q1 is turned-off. Once voltage VG1 reaches zero, voltage VGS2 increases and synchronous rectifier S2 is turned-on at zero voltage VS2 after time td2. Note that during time tb, voltage VG1 is falling while voltage VP is at VIN/2. In practical realization, the voltage remains positive at VIN/2 until VG1 drops to zero. During time tx, the output inductor current is split between the two secondary windings and conducting synchronous rectifiers S1 and S2 causing near zero voltage across all windings of transformer T2.
At t=TS/2, signal OUTB becomes high, while signal OUTA is low. At the same moment, voltage VGS1 starts dropping and when it drops to zero, voltage VG2 starts rising. After time tc, voltage VG2 reaches the threshold voltage of Q2 and Q2 is turned-on. At that moment, voltage VP starts falling to its negative value VIN/2. Note that during time tc, voltage VP is still zero (shorted by the output inductor current flowing in both secondary windings NS1 and NS2 in opposite directions). During time tn, power is transferred from the input to the output of the converter through switch Q2, primary winding Np, secondary winding NS2, synchronous rectifier S2, and output inductor Lo.
At t=TS/2+DTs/2, signal OUTB becomes zero (logic low), signal OUTA is still low, voltage VG2 starts falling and after time td reaches the turn-off threshold of switch Q2, and Q2 is turned-off. Once voltage VG2 reaches zero, voltage VGS1 increases and synchronous rectifier S1 is turned-on at zero voltage VS1 after time td4. Note that during time td, voltage VG2 is falling while voltage VP is at −VIN/2. In practical realization, the voltage remains negative at −VIN/2 until VG2 drops to zero. During time ty (usually tx=ty), the output inductor current is split between the two secondary windings and conducting synchronous rectifiers S1 and S2, causing near zero voltage across all windings of transformer T2.
As is now apparent to those of skill in the art, during turn-on of primary switches Q1 and Q2, the windings of power isolation transformer T1 are shorted (time intervals tx and ty, respectively in FIG. 2). On contrary, during turn-off of primary switches Q1 and Q2 (time intervals tb and td, respectively in FIG. 2) the windings of power isolation transformer T1 are not shorted. This is the main reason that prevents using windings on power transformer T1 to control turn-on and turn-off transitions of the primary switches. Voltage Vp is controlled by turning-on and turning-off of the primary switches. Thus, a change in voltage VP across the winding NP2 of the transformer T1 occurs after the primary switches are turned-on and turned-off. Therefore, it is necessary to have a separate drive transformer for driving the primary switches.
FIG. 3 shows a prior art half-bridge converter with practical implementation of a drive transformer T2, primary switches Q1, Q2, as well as synchronous rectifier control circuits. A detailed description of the prior art circuit shown in FIG. 4 is described in U.S. Pat. No. 7,102,898 B2 by Brkovic. Drive transformer T2 is implemented as a separate component with windings integrated in the PCB. This implementation has advantages over a solution with windings wound around the magnetic core because it provides better repeatability and control of leakage inductance and capacitance of the drive transformer. Thus, better control of the required timing between the drive signals for primary switches and synchronous rectifiers is achieved.
Even though the circuit of FIG. 4 has advantages, in applications where high power density and small size are needed, the only way to reduce the size of drive transformer T2 is to increase the switching frequency. This has a negative effect on the overall efficiency of the converter. In applications that require extremely high efficiency of the converter for a given size, operation at lower switching frequencies is needed which increases the size of the power transformer and output inductor. This leaves no room on the circuit board for a separate drive transformer or any other solutions for isolating the drive signals between the input and output of the converter, such as fast opto-couplers or opto-isolators.
Therefore, what is needed is new solution that eliminates the use of a separate drive transformer or other components for providing isolation for drive signals between the input and output sides of the converter.